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» The Interaction of Architecture and Operating System Design
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98
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FGCS
2002
153views more  FGCS 2002»
14 years 9 months ago
HARNESS fault tolerant MPI design, usage and performance issues
Initial versions of MPI were designed to work efficiently on multi-processors which had very little job control and thus static process models. Subsequently forcing them to suppor...
Graham E. Fagg, Jack Dongarra
EUROSYS
2008
ACM
15 years 6 months ago
30 seconds is not enough!: a study of operating system timer usage
The basic system timer facilities used by applications and OS kernels for scheduling timeouts and periodic activities have remained largely unchanged for decades, while hardware a...
Simon Peter, Andrew Baumann, Timothy Roscoe, Paul ...
GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 4 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
103
Voted
DAC
2005
ACM
15 years 10 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha