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132
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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 7 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
102
Voted
CORR
2006
Springer
91views Education» more  CORR 2006»
15 years 3 months ago
Improved results for a memory allocation problem
We consider a memory allocation problem. This problem can be modeled as a version of bin packing where items may be split, but each bin may contain at most two (parts of) items. T...
Leah Epstein, Rob van Stee
SSS
2010
Springer
128views Control Systems» more  SSS 2010»
15 years 1 months ago
On Transactional Scheduling in Distributed Transactional Memory Systems
We present a distributed transactional memory (TM) scheduler called Bi-interval that optimizes the execution order of transactional operations to minimize conflicts. Bi-interval c...
Junwhan Kim, Binoy Ravindran
121
Voted
ICASSP
2011
IEEE
14 years 7 months ago
Syllabification of conversational speech using Bidirectional Long-Short-Term Memory Neural Networks
Segmentation of speech signals is a crucial task in many types of speech analysis. We present a novel approach at segmentation on a syllable level, using a Bidirectional Long-Shor...
Christian Landsiedel, Jens Edlund, Florian Eyben, ...
133
Voted
ICPR
2006
IEEE
16 years 4 months ago
Face Recognition by Combining Kernel Associative Memory and Gabor Transforms
Kernel associative memory (KAM) has previously been proposed as an efficient scheme for face recognition. In this paper, a hybrid method of combining KAM and Gabor wavelet transfo...
Bailing Zhang, Clement Leung, Yongsheng Gao