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IWNAS
2006
IEEE
15 years 9 months ago
A Fast Read/Write Process to Reduce RDMA Communication Latency
RDMA reduces network latency by eliminating unnecessary copies from network interface cards to application buffers, but how to reduce memory registration cost is a challenge. Prev...
Li Ou, Jizhong Han
NCA
2005
IEEE
15 years 9 months ago
Fundamental Network Processor Performance Bounds
In this paper, fundamental conditions which bound the network processing unit (NPU) worst-case performance are established. In particular, these conditions formalize and integrate...
Hao Che, Chethan Kumar, Basavaraj Menasinahal
SIGOPSE
1998
ACM
15 years 8 months ago
MMLite: a highly componentized system architecture
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
Johannes Helander, Alessandro Forin
CONCUR
2009
Springer
15 years 7 months ago
Weak Time Petri Nets Strike Back!
We consider the model of Time Petri Nets where time is associated with transitions. Two semantics for time elapsing can be considered: the strong one, for which all transitions are...
Pierre-Alain Reynier, Arnaud Sangnier
DAMON
2008
Springer
15 years 5 months ago
Avoiding version redundancy for high performance reads in temporal databases
A major performance bottleneck for database systems is the memory hierarchy. The performance of the memory hierarchy is directly related to how the content of disk pages maps to t...
Khaled Jouini, Geneviève Jomier