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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 5 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
3DGIS
2006
Springer
15 years 5 months ago
3D Geometries in Spatial DBMS
Database management systems (DBMS) have significantly changed in the last several years. From a system dealing with management of administrative data they have involved to a spati...
Sisi Zlatanova
CODES
2005
IEEE
15 years 5 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CASES
2004
ACM
15 years 5 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
NORDICHI
2004
ACM
15 years 5 months ago
Facilitating user interface adaptation to mobile devices
One vision of a context-aware pervasive networking environment promises the user a seamless access to surrounding services using her personal mobile device. This requires that the...
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