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GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
15 years 11 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 11 months ago
Interconnect Planning with Local Area Constrained Retiming
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and ï¬...
Ruibing Lu, Cheng-Kok Koh
INFOCOM
2003
IEEE
15 years 11 months ago
Detecting Network Intrusions via Sampling: A Game Theoretic Approach
In this paper, we consider the problem of detecting an intruding packet in a communication network. Detection is accomplished by sampling a portion of the packets transiting selec...
Murali S. Kodialam, T. V. Lakshman
IPPS
1998
IEEE
15 years 10 months ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
FLAIRS
2007
15 years 8 months ago
Temporal Networks with Alternatives: Complexity and Model
Temporal Networks play an important role in solving planning problems and they are also used, though not as frequently, when solving scheduling problems. In this paper we propose ...
Roman Barták, Ondrej Cepek