20 search results - page 2 / 4 » The Master-Slave Paradigm with Heterogeneous Processors |
APCSAC
2006
IEEE
14 years 9 days ago
2006
IEEE
The systolic array paradigm has low communication demand because it does not use costly global communication and each processor communicates with few other processors. It is thus s...
DSD
2011
IEEE
12 years 6 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
DATE
2006
IEEE
14 years 9 days ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
EUROPAR
2009
Springer
14 years 25 days ago
2009
Springer
While general-purpose homogeneous multi-core architectures are becoming ubiquitous, there are clear indications that, for a number of important applications, a better performance/p...