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IEEEPACT
2007
IEEE
15 years 9 months ago
Verification-Aware Microprocessor Design
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
Anita Lungu, Daniel J. Sorin
130
Voted
ISCAS
2007
IEEE
114views Hardware» more  ISCAS 2007»
15 years 9 months ago
On the Suitability of Discrete-Time Receivers for Software-Defined Radio
—CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been p...
Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta
ISVLSI
2007
IEEE
151views VLSI» more  ISVLSI 2007»
15 years 9 months ago
Design of a MCML Gate Library Applying Multiobjective Optimization
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg...
QEST
2007
IEEE
15 years 9 months ago
Symbolic Bisimulations for Probabilistic Systems
The paper introduces symbolic bisimulations for a simple probabilistic π-calculus to overcome the infinite branching problem that still exists in checking ground bisimulations b...
Peng Wu 0002, Catuscia Palamidessi, Huimin Lin
130
Voted
RTCSA
2007
IEEE
15 years 9 months ago
Fast Schedulability Analysis Using Commodity Graphics Hardware
In this paper we explore the possibility of using commodity graphics processing units (GPUs) to speedup standard schedulability analysis algorithms. Our long-term goal is to explo...
Jimin Feng, Samarjit Chakraborty, Bertil Schmidt, ...