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ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
15 years 6 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
15 years 4 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...
CSE
2008
IEEE
14 years 10 months ago
A High-Throughput Multi-cluster NoC Architecture
During the last years a large number of research works has focused on problems related to multi-core processors. Due to the possibilities of many cores, the number of opportunitie...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
ECBS
2005
IEEE
110views Hardware» more  ECBS 2005»
15 years 3 months ago
Synthesis of C++ Software from Verifiable CSPm Specifications
CSP++ is an object-oriented application framework for execution of CSP specifications that have been automatically synthesized into C++ source code by the cspt translator. We desc...
Stephen Doxsee, William B. Gardner
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
15 years 4 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind