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CF
2006
ACM
15 years 6 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
135
Voted
CGO
2003
IEEE
15 years 6 months ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith
FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 5 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 5 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
90
Voted
BMCBI
2007
102views more  BMCBI 2007»
15 years 27 days ago
Multivariate Analysis and Visualization of Splicing Correlations in Single-Gene Transcriptomes
Background: RNA metabolism, through 'combinatorial splicing', can generate enormous structural diversity in the proteome. Alternative domains may interact, however, with...
Mark C. Emerick, Giovanni Parmigiani, William S. A...