1542 search results - page 178 / 309 » The Observational Power of Clocks |
148
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LFCS
2009
Springer
15 years 7 months ago
2009
Springer
Memory logics are a family of modal logics in which standard relational structures are augmented with data structures and additional operations to modify and query these structure...
89
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ISVLSI
2008
IEEE
15 years 7 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
101
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EMSOFT
2007
Springer
15 years 7 months ago
2007
Springer
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
124
Voted
IEEEPACT
2006
IEEE
15 years 6 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
111
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ISCA
2006
IEEE
15 years 6 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...