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» The Observational Power of Clocks
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ASPDAC
1999
ACM
135views Hardware» more  ASPDAC 1999»
15 years 1 months ago
A High Speed and Low Power Phase-Frequency Detector and Charge - pump
– In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D f...
Won Hyo Lee, Jun Dong Cho, Sung Dae Lee
CODES
2007
IEEE
15 years 4 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
ECAI
2010
Springer
14 years 10 months ago
The Complexity of Epistemic Model Checking: Clock Semantics and Branching Time
In the clock semantics for epistemic logic, two situations are indistinguishable for an agent when it makes the same observation and the time in the situations is the same. The pa...
Xiaowei Huang, Ron van der Meyden
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems
This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a s...
Zhiyi Yu, Bevan M. Baas
DAC
2005
ACM
14 years 11 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty