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» The Observational Power of Clocks
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ACSD
2006
IEEE
81views Hardware» more  ACSD 2006»
15 years 3 months ago
Monitoring and fault-diagnosis with digital clocks
We study the monitoring and fault-diagnosis problems for dense-time real-time systems, where observers (monitors and diagnosers) have access to digital rather than analog clocks. ...
Karine Altisen, Franck Cassez, Stavros Tripakis
ISCAS
2008
IEEE
114views Hardware» more  ISCAS 2008»
15 years 4 months ago
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
Md. Ibrahim Faisal, Magdy A. Bayoumi
DATE
1998
IEEE
76views Hardware» more  DATE 1998»
15 years 1 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram
ICNP
2009
IEEE
15 years 4 months ago
Accurate Clock Synchronization for IEEE 802.11-Based Multi-Hop Wireless Networks
—Clock synchronization is an essential building block for many control mechanisms used in wireless networks, including frequency hopping, power management, and packet scheduling....
Jui-Hao Chiang, Tzi-cker Chiueh
GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
15 years 3 months ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...