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» The Observational Power of Clocks
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TCAD
2010
116views more  TCAD 2010»
14 years 4 months ago
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
Anand Rajaram, David Z. Pan
84
Voted
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
15 years 4 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
ISVLSI
2008
IEEE
125views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Energy Recovery from High-Frequency Clocks Using DC-DC Converters
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Sha...
ISLPED
1995
ACM
134views Hardware» more  ISLPED 1995»
15 years 1 months ago
High-throughput and low-power DSP using clocked-CMOS circuitry
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
63
Voted
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
15 years 3 months ago
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
Xiang Gao, Eric A. M. Klumperink, Bram Nauta