1542 search results - page 23 / 309 » The Observational Power of Clocks |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
TVLSI
2010
14 years 4 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
63
Voted
ESSCIRC
2011
13 years 9 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...