1542 search results - page 24 / 309 » The Observational Power of Clocks |
84
Voted
FPT
2005
IEEE
15 years 3 months ago
2005
IEEE
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
ICC
2007
IEEE
15 years 4 months ago
2007
IEEE
—In this paper the Cramér-Rao lower bound (CRLB) of an ultra-wideband (UWB) pulse amplitude modulated (PAM) signal with time hopping (TH) code is derived for the practical case ...
73
Voted
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract—Low-power, single-chip integrated systems are prevailing in remote applications due to the increasing power and delay cost of inter-chip communication compared to on-chi...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
As the hardware and software complexity grows, it is unlikely for the power management hardware/software to have a full observation of the entire system status. In this paper, we ...