1542 search results - page 25 / 309 » The Observational Power of Clocks |
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
ICCD
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
ISLPED
1999
ACM
15 years 2 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
101
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TIM
2010
14 years 4 months ago
2010
In the last few years, the growing complexity of the electrical power networks, mainly due to the increased use of electronic converters together with the requirements of a higher ...