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» The Observational Power of Clocks
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72
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GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...
79
Voted
INFOCOM
2002
IEEE
15 years 2 months ago
Power-Saving Protocols for IEEE 802.11-Based Multi-Hop Ad Hoc Networks
—Power-saving is a critical issue for almost all kinds of portable devices. In this paper, we consider the design of power-saving protocols for mobile ad hoc networks (MANETs) th...
Yu-Chee Tseng, Chih-Shun Hsu, Ten-Yueng Hsieh
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
15 years 4 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
15 years 3 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
15 years 3 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu