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» The Observational Power of Clocks
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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
15 years 4 months ago
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
Anshuman Chandra, Felix Ng, Rohit Kapur
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
15 years 2 months ago
New clock-gating techniques for low-power flip-flops
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
Antonio G. M. Strollo, E. Napoli, Davide De Caro
PODC
1997
ACM
15 years 1 months ago
Lazy Consistency Using Loosely Synchronized Clocks
Thispaperdescribesanewschemeforguaranteeingthattransactions in a client/server system observe consistent state while they are running. The scheme is presented in conjunction with ...
Atul Adya, Barbara Liskov
BIBM
2008
IEEE
15 years 4 months ago
Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock
Abstract—Biological clock, a self sustaining oscillation widely discovered in many species, is important to determine many biological activities, for example, the sleep-wake cycl...
Peng Yu, Xi Chen, David Z. Pan, Andrew D. Ellingto...