1542 search results - page 34 / 309 » The Observational Power of Clocks |
DAC
2007
ACM
15 years 1 months ago
2007
ACM
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated ...
70
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
141
Voted
FDTC
2011
Springer
13 years 9 months ago
2011
Springer
Abstract—The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on som...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
We examine noise due to clock jitter in single-loop low pass continuous-time delta-sigma modulators employing NRZ feedback DACs. Using the discrete-time version of the Bode sensit...