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» The Observational Power of Clocks
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ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
15 years 1 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
84
Voted
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
CCS
2006
ACM
15 years 1 months ago
Hot or not: revealing hidden services by their clock skew
Location-hidden services, as offered by anonymity systems such as Tor, allow servers to be operated under a pseudonym. As Tor is an overlay network, servers hosting hidden service...
Steven J. Murdoch
DAC
2001
ACM
15 years 10 months ago
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
Jafar Savoj, Behzad Razavi