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» The Observational Power of Clocks
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35
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ASPDAC
2004
ACM
92views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Modeling of coplanar waveguide for buffered clock tree
—Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. In this paper, we first propose a piece-wise l...
Jun Chen, Lei He
86
Voted
ICISC
2009
132views Cryptology» more  ICISC 2009»
14 years 7 months ago
Side-Channel Analysis of Cryptographic Software via Early-Terminating Multiplications
Abstract. The design of embedded processors demands a careful tradeoff between many conflicting objectives such as performance, silicon area and power consumption. Finding such a t...
Johann Großschädl, Elisabeth Oswald, Da...
86
Voted
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 3 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
15 years 6 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...
SENSYS
2009
ACM
15 years 2 months ago
A tale of two synchronizing clocks
A specific application for wastewater monitoring and actuation, called CSOnet, deployed city-wide in a mid-sized US city, South Bend, Indiana, posed some challenges to a time syn...
Jinkyu Koo, Rajesh Krishna Panta, Saurabh Bagchi, ...