1542 search results - page 47 / 309 » The Observational Power of Clocks |
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
DDECS
2009
IEEE
15 years 4 months ago
2009
IEEE
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
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VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
IPSN
2010
Springer
15 years 4 months ago
2010
Springer
We present Virtual High-resolution Time (VHT), a powerproportional time-keeping service that offers a baseline power draw of a low-speed clock (e.g. 32 kHz crystal), but provides...