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FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
15 years 4 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...
DSD
2006
IEEE
183views Hardware» more  DSD 2006»
15 years 3 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
HOTI
2005
IEEE
15 years 3 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
IANDC
2008
87views more  IANDC 2008»
14 years 9 months ago
Timed Petri nets and timed automata: On the discriminating power of zeno sequences
Timed Petri nets and timed automata are two standard models for the analysis of real-time systems. In this paper, we prove that they are incomparable for the timed language equival...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
SIPS
2006
IEEE
15 years 3 months ago
Low Power Trellis Decoder with Overscaled Supply Voltage
Abstract— This paper is interested in applying voltage overscaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding perform...
Yang Liu, Tong Zhang, Jiang Hu