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» The Observational Power of Clocks
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RECOMB
2005
Springer
15 years 10 months ago
Very Low Power to Detect Asymmetric Divergence of Duplicated Genes
Abstract. Asymmetric functional divergence of paralogues is a key aspect of the traditional model of evolution following duplication. If one gene continues to perform the ancestral...
Cathal Seoighe, Konrad Scheffler
OPODIS
2003
14 years 11 months ago
Linear Time Byzantine Self-Stabilizing Clock Synchronization
Awareness of the need for robustness in distributed systems increases as distributed systems become an integral part of day-to-day systems. Tolerating Byzantine faults and possessi...
Ariel Daliot, Danny Dolev, Hanna Parnas
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
15 years 4 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ASPDAC
2012
ACM
247views Hardware» more  ASPDAC 2012»
13 years 5 months ago
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
Xin Zhao, Sung Kyu Lim
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
15 years 6 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha