1542 search results - page 60 / 309 » The Observational Power of Clocks |
SIGMETRICS
2010
ACM
15 years 2 months ago
2010
ACM
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...