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ICON
2007
IEEE
15 years 4 months ago
An Approximate Analysis of the Balance among Performance, Utilization and Power Estimation of Server Systems by Use of the Batch
- In this paper we analyze the performance, utilization, and power estimation of server systems by both adopting the batch service and adjusting the batch size. In addition to redu...
Ying-Wen Bai, Yung-Sen Cheng, Cheng-Hung Tsai
EUC
2006
Springer
15 years 1 months ago
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
Wann-Yun Shieh, Hsin-Dar Chen
CDES
2006
240views Hardware» more  CDES 2006»
14 years 11 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
VLSISP
2011
216views Database» more  VLSISP 2011»
14 years 4 months ago
Accurate Area, Time and Power Models for FPGA-Based Implementations
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Cha...
ISCAS
2007
IEEE
78views Hardware» more  ISCAS 2007»
15 years 4 months ago
Towards Automated Power Gating of Registers using CoDeL
— In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we e...
Nainesh Agarwal, Nikitas J. Dimopoulos