Sciweavers

1542 search results - page 62 / 309
» The Observational Power of Clocks
Sort
View
SAMOS
2007
Springer
15 years 3 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
CODES
2008
IEEE
15 years 4 months ago
System-level mitigation of WID leakage power variability using body-bias islands
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
Siddharth Garg, Diana Marculescu
AINA
2007
IEEE
15 years 4 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
LCPC
2005
Springer
15 years 3 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
15 years 3 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf