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DATE
2005
IEEE
98views Hardware» more  DATE 2005»
15 years 3 months ago
Hardware Accelerated Power Estimation
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
ISQED
2005
IEEE
162views Hardware» more  ISQED 2005»
15 years 3 months ago
Controlled-Load Limited Switch Dynamic Logic Circuit
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
ASPDAC
2004
ACM
101views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A sub-mW MPEG-4 motion estimation processor core for mobile video application
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the...
Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, K...
ISCA
2002
IEEE
80views Hardware» more  ISCA 2002»
15 years 2 months ago
A Large, Fast Instruction Window for Tolerating Cache Misses
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson K...
81
Voted
ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
15 years 6 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....