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DAC
1998
ACM
15 years 2 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
HPCA
1999
IEEE
15 years 2 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
IPSN
2007
Springer
15 years 4 months ago
Micro power meter for energy monitoring of wireless sensor networks at scale
We present SPOT, a scalable power observation tool that enables in situ measurement of nodal power and energy over a dynamic range exceeding four decades or a temporal resolution ...
Xiaofan Jiang, Prabal Dutta, David E. Culler, Ion ...
ASAP
2008
IEEE
182views Hardware» more  ASAP 2008»
15 years 4 months ago
Low-cost implementations of NTRU for pervasive security
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design ...
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid V...
APCCAS
2006
IEEE
296views Hardware» more  APCCAS 2006»
15 years 3 months ago
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekin...