Sciweavers

1542 search results - page 75 / 309
» The Observational Power of Clocks
Sort
View
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
15 years 3 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
IEICET
2008
117views more  IEICET 2008»
14 years 10 months ago
Direct-Sequence/Spread-Spectrum Communication System with Sampling Rate Selection Diversity
In this paper, sampling rate selection diversity (SRSD) scheme for Direct-Sequence / Spread-Spectrum (DS/SS) is proposed. In DS/SS communication systems, oversampling may be employ...
Yohei Suzuki, Anas Muhamad Bostamam, Mamiko Inamor...
ACISP
2006
Springer
15 years 3 months ago
Distinguishing Attack on SOBER-128 with Linear Masking
Abstract. We present a distinguishing attack against SOBER-128 with linear masking. We found a linear approximation which has a bias of 2−8.8 for the non-linear filter. The atta...
Joo Yeon Cho, Josef Pieprzyk
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
15 years 3 months ago
A Fourier series-based RLC interconnect model for periodic signals
— Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far end time ...
Guoqing Chen, Eby G. Friedman
72
Voted
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 3 months ago
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs
We present a visualization tool called PLFire, which allows a user to observe the behavior of a Phased Logic (PL) circuit. Phased logic is a technique for realizing self-timed cir...
Kenneth Fazel, Mitchell A. Thornton, Robert B. Ree...