This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
In this paper, sampling rate selection diversity (SRSD) scheme for Direct-Sequence / Spread-Spectrum (DS/SS) is proposed. In DS/SS communication systems, oversampling may be employ...
Yohei Suzuki, Anas Muhamad Bostamam, Mamiko Inamor...
Abstract. We present a distinguishing attack against SOBER-128 with linear masking. We found a linear approximation which has a bias of 2−8.8 for the non-linear filter. The atta...
— Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far end time ...
We present a visualization tool called PLFire, which allows a user to observe the behavior of a Phased Logic (PL) circuit. Phased logic is a technique for realizing self-timed cir...
Kenneth Fazel, Mitchell A. Thornton, Robert B. Ree...