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» The Packet Switching Brain
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FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
15 years 3 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
INFOCOM
2005
IEEE
15 years 3 months ago
Credit based fair scheduling for packet switched networks
With the rapid development of Internet multimedia applications, the next generation of networks is required to schedule not only the best effort traffic but also the traffic wit...
Deng Pan, Yuanyuan Yang
INFOCOM
2003
IEEE
15 years 2 months ago
A Petabit Photonic Packet Switch (P3S)
H. Jonathan Chao, Kung-Li Deng, Zhigang Jing
GCC
2003
Springer
15 years 2 months ago
Maintaining Packet Order for the Parallel Switch
Yuguo Dong, Binqiang Wang, Yunfei Guo, Jiangxing W...