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» The Packet Switching Brain
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FPL
2003
Springer
136views Hardware» more  FPL 2003»
15 years 2 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
AI
2004
Springer
14 years 9 months ago
Brain-actuated interaction
Over the last years evidence has accumulated that shows the possibility to analyze human brain activity on-line and translate brain states into actions such as selecting a letter ...
José del R. Millán, Fréd&eacu...
DAC
2006
ACM
15 years 10 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
LATIN
1998
Springer
15 years 1 months ago
Dynamic Packet Routing on Arrays with Bounded Buffers
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
Andrei Z. Broder, Alan M. Frieze, Eli Upfal
NIPS
1993
14 years 11 months ago
Packet Routing in Dynamically Changing Networks: A Reinforcement Learning Approach
This paper describes the Q-routing algorithm for packet routing, in which a reinforcement learning module is embedded into each node of a switching network. Only local communicati...
Justin A. Boyan, Michael L. Littman