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» The Packet Switching Brain
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IPPS
2003
IEEE
15 years 10 months ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu
HOTI
2005
IEEE
15 years 10 months ago
Design and Implementation of a Content-Aware Switch Using a Network Processor
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. ...
INFOCOM
2000
IEEE
15 years 9 months ago
Design, Implementation and Performance of a Content-Based Switch
Abstract— In this paper, we share our experience in designing and building a content based switch which we call L5. In addition to the layer 2-3-4 information available in the pa...
George Apostolopoulos, David Aubespin, Vinod G. J....
INFOCOM
2010
IEEE
15 years 2 months ago
Haste: Practical Online Network Coding in a Multicast Switch
The use of network coding has been shown to improve throughput in input-queued multicast switches, but not without costs of computational complexity and delays. In this paper, we i...
Shuang Yang, Xin Wang, Baochun Li
RTSS
2006
IEEE
15 years 11 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...