Sciweavers

506 search results - page 51 / 102
» The Packet Switching Brain
Sort
View
INFOCOM
2010
IEEE
14 years 8 months ago
Enabling a Bufferless Core Network Using Edge-to-Edge Packet-Level FEC
— Internet traffic is expected to grow phenomenally over the next five to ten years, and to cope with such large traffic volumes, core networks are expected to scale to capaci...
Arun Vishwanath, Vijay Sivaraman, Marina Thottan, ...
SIGCOMM
1995
ACM
15 years 1 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
INFOCOM
2006
IEEE
15 years 3 months ago
Optimal Scheduling Algorithms for Input-Queued Switches
— The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high line speeds. A central problem in designing an input-queued swit...
Devavrat Shah, Damon Wischik
ANOR
2008
112views more  ANOR 2008»
14 years 10 months ago
Analysis of a tandem network model of a single-router Network-on-Chip
We study a single-router Network-on-Chip modelled as a tandem queueing network. The first node is a geoK /D/1 queue (K fixed) representing a network interface, and the second node...
Paul Beekhuizen, Dee Denteneer, Ivo J. B. F. Adan
CCR
2006
92views more  CCR 2006»
14 years 9 months ago
Flow labelled IP over ATM: design and rationale
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...
Greg Minshall, Robert M. Hinden, Eric Hoffman, Fon...