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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 2 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
GLOBECOM
2006
IEEE
15 years 3 months ago
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
Rongsen He, José G. Delgado-Frias
INFOCOM
2006
IEEE
15 years 3 months ago
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
Nikolaos Chrysos, Manolis Katevenis
IPPS
1998
IEEE
15 years 2 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
INFOCOM
1997
IEEE
15 years 2 months ago
Analysis of Queueing Displacement Using Switch Port Speedup
Current high-speed packet switching systems, ATM in particular, have large port bu ering requirements. The use of highly integrated ASIC technology for implementing high-degree an...
Israel Cidon, Asad Khamisy, Moshe Sidi