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» The Performance of Cache-Coherent Ring-based Multiprocessors
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HPCA
2007
IEEE
15 years 3 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
ICPP
1990
IEEE
15 years 1 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
DSD
2008
IEEE
147views Hardware» more  DSD 2008»
14 years 11 months ago
A Low-Cost Cache Coherence Verification Method for Snooping Systems
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
Demid Borodin, Ben H. H. Juurlink
MAM
2002
151views more  MAM 2002»
14 years 9 months ago
A performance evaluation of cache injection in bus-based shared memory multiprocessors
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
Aleksandar Milenkovic, Veljko M. Milutinovic
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
15 years 3 months ago
Coherence Ordering for Ring-based Chip Multiprocessors
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched inter...
Michael R. Marty, Mark D. Hill