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» The Performance of Cache-Coherent Ring-based Multiprocessors
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HIPC
2007
Springer
15 years 3 months ago
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...
Alberto Ros, Manuel E. Acacio, José M. Garc...
CF
2006
ACM
15 years 1 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
LCN
2000
IEEE
15 years 1 months ago
Reliability Modeling of SCI Ring-Based Topologies
Performance evaluation and reliability prediction are two important factors in the study of multiprocessor and cluster interconnects. One such interconnect is the Scalable Coheren...
M. A. Sarwar, Alan D. George, David E. Collins
PACT
2007
Springer
15 years 3 months ago
Support for Fine-Grained Synchronization in Shared-Memory Multiprocessors
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
Vladimir Vlassov, Oscar Sierra Merino, Csaba Andra...
ASPLOS
2008
ACM
14 years 11 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...