49 search results - page 7 / 10 » The Performance of Cache-Coherent Ring-based Multiprocessors |
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...
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ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
SIGMETRICS
1996
ACM
15 years 1 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
FGCS
2006
14 years 9 months ago
2006
The choice of an interconnection network for a parallel computer depends on a large number of performance factors which are very often application dependent. We propose a performa...