A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
—When shortest path routing is employed in large scale multi-hop wireless networks, nodes located near the center of the network have to perform disproportional amount of relayin...
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
— Feedback of channel state information (CSI) enables a multi-carrier transmitter to optimize the power allocation across sub-channels. We consider a single user feedback scheme ...