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DAC
1998
ACM
15 years 2 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ICDCS
2008
IEEE
15 years 4 months ago
Fully Adaptive Power Saving Protocols for Ad Hoc Networks Using the Hyper Quorum System
Quorum-based Power Saving (QPS) protocols have been proposed for ad hoc networks (e.g., IEEE 802.11 ad hoc mode) to increase energy efficiency and prolong the operational time of...
Shan-Hung Wu, Ming-Syan Chen, Chung-Min Chen
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
15 years 6 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
CGO
2005
IEEE
15 years 3 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
CN
2007
129views more  CN 2007»
14 years 10 months ago
Performance evaluation of MAC transmission power control in wireless sensor networks
In this paper we provide a method to analytically compute the energy saving provided by the use of transmission power control (TPC) at the MAC layer in wireless sensor networks (W...
Javier Vales-Alonso, Esteban Egea-López, Al...