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DAC
2000
ACM
15 years 11 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
DAC
1997
ACM
15 years 2 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
SIGCOMM
2010
ACM
14 years 10 months ago
Helios: a hybrid electrical/optical switch architecture for modular data centers
The basic building block of ever larger data centers has shifted from a rack to a modular container with hundreds or even thousands of servers. Delivering scalable bandwidth among...
Nathan Farrington, George Porter, Sivasankar Radha...
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
15 years 4 months ago
Quasi-Resonant Interconnects: A Low Power Design Methodology
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
Jonathan Rosenfeld, Eby G. Friedman
ISLPED
1998
ACM
95views Hardware» more  ISLPED 1998»
15 years 2 months ago
The petrol approach to high-level power estimation
High-level power estimation is essential for designing complex low-power ICs. However, the lack of flexibility, or restriction to synthesizable code of previously presented high-...
Rafael Peset Llopis, Kees G. W. Goossens