This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
—We address the issue of power-controlled shared channel access in future wireless networks supporting packetized data traffic, beyond the voice-oriented continuous traffic prima...
In this paper, we study the problem of transmission power control and its effects on the link-scheduling performance when a set of end-to-end flows established in the network are g...
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...