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VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
15 years 10 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 2 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
INFOCOM
2000
IEEE
15 years 2 months ago
Power Controlled Multiple Access (PCMA) in Wireless Communication Networks
—We address the issue of power-controlled shared channel access in future wireless networks supporting packetized data traffic, beyond the voice-oriented continuous traffic prima...
Nicholas Bambos, Sunil Kandukuri
GLOBECOM
2010
IEEE
14 years 7 months ago
Queue-Stability-Based Transmission Power Control in Wireless Multihop Networks
In this paper, we study the problem of transmission power control and its effects on the link-scheduling performance when a set of end-to-end flows established in the network are g...
Gustavo Vejarano, Janise McNair
AHS
2007
IEEE
349views Hardware» more  AHS 2007»
15 years 4 months ago
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
Mustafa Parlak, Ilker Hamzaoglu