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ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
15 years 2 months ago
Instruction level power model of microcontrollers
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
C. Chakrabarti, D. Gaitonde
CHES
2006
Springer
74views Cryptology» more  CHES 2006»
15 years 1 months ago
Optically Enhanced Position-Locked Power Analysis
Abstract. This paper introduces a refinement of the power-analysis attack on integrated circuits. By using a laser to illuminate a specific area on the chip surface, the current th...
Sergei P. Skorobogatov
DAC
1995
ACM
15 years 1 months ago
Register Allocation and Binding for Low Power
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
Jui-Ming Chang, Massoud Pedram
ICC
2007
IEEE
108views Communications» more  ICC 2007»
15 years 4 months ago
Achieving High Goodput Performance in Mars Missions through Application Layer Coding and Transmission Power Trading
— Transferring data reliably from Mars to Earth stations is becoming an appealing challenge in the design of interplanetary networks. In this view, the use of CCSDS-based protoco...
Tomaso de Cola, Harald Ernst, Mario Marchese