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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
15 years 3 months ago
Low power SRAM techniques for handheld products
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
Rabiul Islam, Adam Brand, Dave Lippincott
IM
2007
14 years 9 months ago
Using the Power of Two Choices to Improve Bloom Filters
We consider the combination of two ideas from the hashing literature: the power of two choices and Bloom filters. Specifically, we show via simulations that, in comparison with a...
Steven S. Lumetta, Michael Mitzenmacher
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
14 years 8 months ago
Combining optimizations in automated low power design
—Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
Qiang Liu, Tim Todman, Wayne Luk
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 9 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
15 years 4 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...