Sciweavers

614 search results - page 86 / 123
» The Power of Methods With Parallel Semantics
Sort
View
IEEEPACT
2002
IEEE
15 years 10 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
IPPS
2010
IEEE
15 years 2 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
ASPLOS
2009
ACM
16 years 5 months ago
Optimization of tele-immersion codes
As computational power increases, tele-immersive applications are an emerging trend. These applications make extensive demands on computational resources through their heavy use o...
Albert Sidelnik, I-Jui Sung, Wanmin Wu, Marí...
HPCA
2005
IEEE
16 years 5 months ago
Distributing the Frontend for Temperature Reduction
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
Antonio González, Grigorios Magklis, Jos&ea...
SLIP
2004
ACM
15 years 10 months ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor