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» The Power of One Move: Hashing Schemes for Hardware
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MICRO
2000
IEEE
74views Hardware» more  MICRO 2000»
15 years 1 months ago
A framework for dynamic energy efficiency and temperature management
While technology is delivering increasingly sophisticated and powerful chip designs, it is also imposing alarmingly high energy requirements on the chips. One way to address this ...
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Jose...
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
14 years 7 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
76
Voted
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
15 years 3 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
154
Voted
ASPLOS
2009
ACM
15 years 10 months ago
Capo: a software-hardware interface for practical deterministic multiprocessor replay
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
Pablo Montesinos, Matthew Hicks, Samuel T. King, J...
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
15 years 4 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim