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» The Power of One Move: Hashing Schemes for Hardware
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PACS
2004
Springer
115views Hardware» more  PACS 2004»
15 years 3 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
81
Voted
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 3 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
EUC
2007
Springer
15 years 1 months ago
An Efficient Authentication Protocol for RFID Systems Resistant to Active Attacks
Traditional cryptographic primitives are not supported on low-cost RFID tags since, at most, 4K gates can be devoted to securityrelated tasks. Despite this, there are a vast number...
Pedro Peris-Lopez, Julio César Herná...
ISMVL
2000
IEEE
105views Hardware» more  ISMVL 2000»
15 years 2 months ago
Computational Neurobiology Meets Semiconductor Engineering
Many believe that the most important result to come out of the last ten years of neural network research is the significant change in perspective in the neuroscience community tow...
Dan W. Hammerstrom
77
Voted
IPPS
2010
IEEE
14 years 7 months ago
Profitability-based power allocation for speculative multithreaded systems
With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional outof-order processors, multi-core systems are becoming the design ...
Polychronis Xekalakis, Nikolas Ioannou, Salman Kha...