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ICCD
2007
IEEE
180views Hardware» more  ICCD 2007»
16 years 1 months ago
Improving the reliability of on-chip data caches under process variations
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lie...
110
Voted
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
15 years 11 months ago
ASPA: Focal Plane digital processor array with asynchronous processing capabilities
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
Alexey Lopich, Piotr Dudek
ASPDAC
2004
ACM
130views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Automatic process migration of datapath hard IP libraries
— While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few microprocessor companies. The reusability of dat...
Fang Fang, Jianwen Zhu
TSMC
2010
14 years 11 months ago
Multiobjective Optimization of Temporal Processes
Abstract--This paper presents a dynamic predictiveoptimization framework of a nonlinear temporal process. Datamining (DM) and evolutionary strategy algorithms are integrated in the...
Zhe Song, Andrew Kusiak
ICASSP
2011
IEEE
14 years 8 months ago
A point target reference spectrum for general bistatic SAR processing
Focusing bistatic SAR data in frequency domain requires the two dimensional (2D) point target reference spectrum (PTRS). In this paper, a 2D PTRS is derived based on Loffeld’s b...
Junjie Wu, Jianyu Yang, Yulin Huang, Haiguang Yang...