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MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
15 years 10 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
15 years 9 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
EUROGP
2001
Springer
124views Optimization» more  EUROGP 2001»
15 years 9 months ago
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
Massimiliano Erba, Roberto Rossi, Valentino Libera...
CORR
2011
Springer
162views Education» more  CORR 2011»
14 years 8 months ago
Optimal Power Cost Management Using Stored Energy in Data Centers
Since the electricity bill of a data center constitutes a significant portion of its overall operational costs, reducing this has become important. We investigate cost reduction o...
Rahul Urgaonkar, Bhuvan Urgaonkar, Michael J. Neel...
DAC
2008
ACM
16 years 5 months ago
Feedback-controlled reliability-aware power management for real-time embedded systems
In recent literature it has been reported that Dynamic Power Management (DPM) may lead to decreased reliability in real-time embedded systems. The ever-shrinking device sizes cont...
Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra