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147
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ITC
2003
IEEE
138views Hardware» more  ITC 2003»
15 years 9 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
15 years 2 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
16 years 1 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
CISS
2007
IEEE
15 years 10 months ago
Video Sensor Node for Low-Power Ad-hoc Wireless Networks
A video sensor platform consisting of a smart image sensor with focal plane motion processing is presented. The camera node is intended for ultra-low bandwidth ad-hoc wireless netw...
Yu M. Chi, Ralph Etienne-Cummings, Gert Cauwenberg...
107
Voted
ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
15 years 8 months ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...